Many electrical circuits, particularly those which include MOS transistors, are subject to being damaged by electrostatic discharge (ESD). To overcome this problem, ESD protection circuits have been developed for various types of circuitry. For example, see my U.S. Pat. No. 5,043,782 and my U.S. Pat. No. 5,343,053 and my pending U.S. patent application Ser. No. 08/291,809, each of which is incorporated herein by reference, are particularly applicable to protection of ICs from ESD on the power buss.
To date, ESD protection schemes have addressed the input, output and power ports of an integrated circuit (IC). However, as ICs have grown in size and complexity, and device geometries have shrunk, ESD damage to interconnected array of individual cells, such as an array of macrocells forming core logic circuitry, has become more prevalent. This has been addressed in new designs by adding power supply ESD protection structures to the macrocells' power lines, and providing ESD protection between the input/output (I/O) circuits around the periphery of the IC and the I/O ports of the macro logic cells. Once such a circuit is designed with the various macrocells, such as logic cells, being arranged in a manner so as to form a compact overall device, it is difficult to provide each individual macrocell with power supply ESD protection circuits without a substantial layout effort involving redesign of the logic macrocells, increasing the overall size of the device. In addition, adequate ESD protection for core logic circuitry as a whole requires the application of a set of rules which are often difficult to check using automatic computer routines. Currently, an engineer who is knowledgeable in the art is required to check such a chip layout. Thus, it would be desirable to have a technique for providing the core logic circuits of a large integrated circuit with ESD protection for the core logic circuits as a whole block in a manner in which it is easily computer checked rather than trying to protect each macrocell.